1. Field of the Invention
This invention relates to an EPROM circuit with error correction.
2. Description of the Prior Art
Generally, in EPROMs (Electrically Programmable Read-Only Memory), there is a possibility of occurrence of the unintentionally erasing error due to dispersion in the data maintaining interval of each memory cell (EPROM cell) or noise. That is, bit data may changes from the logic value representing the programmed condition to the logic value representing the unprogrammed condition. Moreover, there is the unintentionally writing error wherein the logical value representing the unprogrammed condition to the unprogrammed condition, though the probability of occurrence of unintentionally writing error is lower than the unintentionally erasing error.
To prevent these errors, an EPROM circuit with correction adopting three-bit majority determination method has been proposed. Japanese patent application provisional publication No. 57-143656 discloses such a prior art EPROM circuit with correction.
FIG. 2 is a block diagram of such a prior art EPROM circuit.
The EPROM circuit of this prior art including a plurality of bit (storing) circuits having output lines, respectively, each including three EPROM cells MA, MB, and MC and a majority determining circuit for determining majority among output values of three EPROM cells MA, MB, and MC and outputting the majority result. The majority is determined such that the same value which is outputted from more than one of the EPROMs is determined as majority.
The majority determining circuit T includes three two-input NOR gates 1 to 3 and three-input NOR gate 4 of which output is connected to each of outputting lines OUT(1) to OUT(n).
In this EPROM circuit with error correction, if more than one outputs of three EPROMs MA, MB, MC are correct, the value can be judged correct.
For example, values stored in the EPROMs MA, MB, MC change from "1, 1, 1" (correct logic values) to either of "0, 1, 1", "1, 0, 1", or "1, 1, 0", all inputs of the three-input NOR gate 4 remains "0", because there is no two-input NOR gate of which both inputs are supplied with "0". Therefore, the correct value of "1" is outputted from the three-input NOR gate 4.
Inversely, values stored in the EPROMs MA, MB, MC change from "0, 0, 0" (correct logic values) to either of "1, 0, 0", "0, 1, 0", or "0, 0, 1" due to the unintentionally writing error, there is at least one of two-input NOR gate of which both inputs remains "0", so that the two-input NOR gate still supplies "1" to the three-input NOR gate 4. Thus, the three-input NOR gate 4 outputs correct value of "0". In this prior art, three EPROMs were necessary for each bit.